1. Field of the Invention
The present invention relates to processes involved in the manufacturing of semiconductor devices on a substrate. More particularly, the present invention relates to new methods for forming antifuses on semiconductor wafers.
2. Description of the Related Art
Integrated circuit devices are commonly designed with redundant components such that a redundant component may be substituted for a defective component discovered during testing. For example, portions of a defective memory array may be repaired by substituting a redundant memory array for the defective one. Using this method, the yield or acceptable rate of chips produced on a wafer may be increased.
Conventional DRAM and SRAM memories often use laser fuse blowing techniques, i.e., blowing one or more fuses with a laser beam to deactivate a defective cell or line. The unblown fuse has a low resistance whereas the blown fuse has a high resistance, typically functioning as an open circuit. But laser techniques are expensive and time consuming. Moreover, the laser energy can damage adjacent areas.
To address these issues, antifuse technology has been introduced. Antifuses typically functionally present an open circuit when unblown, having relatively high resistances (e.g., several mega ohms or more) and relatively low resistances (usually less than 1000 ohms) when blown. Both the fuses and the antifuses may be used to provide one-time programming capability to a circuit.
Antifuses are formed by one of several conventional methods using doped polysilicon layers. For example, according to a first conventional method, an oxide layer is positioned between a first doped polysilicon or metal layer and a second doped polysilicon or metal layer. Typically these antifuse layers are approximately 100 Angstroms thick and require a high voltage to breakdown. For example, such antifuse devices are often located in FPGA's and require an applied electrical voltage of between 10 and 20 volts to activate the antifuse element. Activation in the antifuse context refers to the step of implementing the redundant circuit.
According to a second conventional method, an antifuse element is formed in a doped polysilicon layer, the application of a high (i.e., well above nominal design voltage) converting the high resistivity polysilicon link to a low resistivity type.
Another conventional method places a thin (i.e., 15–25 Angstrom) silicon oxide dielectric layer between conductive electrodes. Charge pumps are used to step up the circuit voltage to about 8 to 10 volts. However, the thin oxide layer often has a very high rate of leakage. Moreover, a large part of the area of the die is consumed by the charge pump.
As described, each of the conventional methods for forming antifuses has certain drawbacks which affect their suitability for semiconductor applications. For each of them, special design considerations, such as including additional circuitry affect the design process, the size of the die, and special requirements such as additional power supply voltages. Accordingly, what is needed is a new method for forming an antifuse that can be easily incorporated into CMOS process flow. That is, not too thick or thin a dielectric layer and a low enough activation voltage to eliminate the charge pump.